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Architecture and methodology of a SoPC with 3.25Gbps CDR based SERDES and 1Gbps dynamic phase alignment.

Ranianand VenkataWilson WongTina TranVinson ChanTim HoangHenry LuiUinh TonSergey ShomurryevChong LeeShoujun WaiigHuy NgoMalik KdhaniVictor MaruriTin LaiTam KpuyeuArch ZaliziiyakMei LuoToan NguyenKazi AsaduzzamanSiniardeep MaangatJohn LamRakesh Patel
Published in: CICC (2003)
Keyphrases
  • multi layer
  • dynamic environments
  • real time
  • design methodology
  • conceptual model
  • software implementation
  • master slave
  • learning algorithm
  • multiscale
  • image registration
  • data flow
  • image alignment