A RISC-V in-network accelerator for flexible high-performance low-power packet processing.
Salvatore Di GirolamoAndreas KurthAlexandru CalotoiuThomas BenzTimo SchneiderJakub BeránekLuca BeniniTorsten HoeflerPublished in: ISCA (2021)
Keyphrases
- low power
- low power consumption
- low cost
- power consumption
- high speed
- real time
- image sensor
- single chip
- processing capabilities
- gigabit ethernet
- field programmable gate array
- signal processor
- network layer
- power saving
- logic circuits
- vlsi circuits
- high power
- communication networks
- network traffic
- digital signal processing
- peer to peer
- vlsi architecture
- cmos technology
- gate array
- packet loss
- energy efficiency
- massively parallel
- data flow
- application specific