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, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology.

Woo-Rham BaeGyu-Seob JeongKwanseo ParkSung-Yong ChoYoonsoo KimDeog-Kyoon Jeong
Published in: IEEE Trans. Circuits Syst. I Regul. Pap. (2016)
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