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4 GHz 130nm Low Voltage PLL Based on Self Biased Technique.
Biju Viswanathan
Vijay Viswam
R. Kulanthaivelu
Joseph J. Vettickatt
S. R. Ramya Nair
Lekshmi S. Chandran
Published in:
VLSI Design (2010)
Keyphrases
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low voltage
cmos technology
leakage current
low power
power consumption
high speed
power line
design considerations
parallel processing
high quality
random access memory
power management
power dissipation
low cost
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