VLSI design of a high-speed RAS crypto-processor with reconfigurable architecture.

Yibo Fan Xiaoyang Zeng Zhang Zhang Jun Chen Qianling Zhang

Published in: ISSPA (2005)

Keyphrases

vlsi design
high speed
reconfigurable architecture
systolic array
low power
design methodology
building blocks
parallel architecture
real time
input output
data flow
error detection
neural network
expert systems
markov random field
efficient implementation