A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS.
Ashkan Roshan-ZamirTakayuki IwaiYang-Hang FanAnkur KumarHae-Woong YangLee SledjeskiJohn HamiltonSoumya ChandramouliArlo AudeSamuel PalermoPublished in: IEEE J. Solid State Circuits (2019)
Keyphrases
- low overhead
- digital filters
- decision feedback
- high speed
- high reliability
- load balancing
- cmos technology
- low cost
- low power
- silicon on insulator
- metal oxide semiconductor
- communication cost
- active contours
- nm technology
- finite impulse response
- shared memory
- energy efficient
- infinite impulse response
- false alarm probability
- error propagation
- filter bank
- scheduling algorithm
- power consumption
- low pass filter
- image sensor
- soft decision
- distributed breakout
- filter design
- real time
- multipath
- distributed systems
- digital libraries
- data sets