-DLM: Cache coherence aware dual link mesh for on-chip interconnect.

Sonal Yadav Vijay Laxmi Manoj Singh Gaur Megha Bhargava

Published in: VDAT (2015)

Keyphrases

high speed
power dissipation
low cost
d mesh
real time
programmable logic
analog vlsi
power consumption
link structure
interconnection networks
evolutionary algorithm
high density
chip design
delaunay triangulation
volumetric data