A 28 nm CMOS Triple-Latch Feed-Forward Dynamic Comparator With <27 ps / 1 V and <70 ps / 0.6 V Delay at 5 mV-Sensitivity.
Athanasios T. RamkajMarcel J. M. PelgromMichiel S. J. SteyaertFilip TavernierPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2022)
Keyphrases
- feed forward
- back propagation
- artificial neural networks
- power consumption
- neural nets
- low power
- neural network
- recurrent neural networks
- hidden layer
- biologically plausible
- feed forward neural networks
- high speed
- low cost
- activation function
- real time
- visual cortex
- cmos technology
- clock gating
- motion vectors
- artificial intelligence
- power dissipation
- neural architecture
- neuron model