A bipartition-codec architecture to reduce power in pipelined circuits.

Shanq-Jang Ruan Rung-Ji Shang Feipei Lai Shyh-Jong Chen Xian-Jun Huang

Published in: ICCAD (1999)

Keyphrases

data flow
power consumption
real time
management system
parallel architecture
multithreading
analog vlsi
high speed
design considerations
power reduction
web services
video coding
design methodology
digital circuits
high level synthesis