A scalable sub-1.2mW 300MHz-to-1.5GHz host-clock PLL for system-on-chip in 32nm CMOS.

Hyung-Jin Lee Alexandra M. Kern Sami Hyvonen Ian A. Young

Published in: ISSCC (2011)

Keyphrases

power consumption
nm technology
clock gating
cmos technology
clock frequency
low power
power dissipation
power reduction
low voltage
high speed
duty cycle
single chip
hd video