Formal verification of an ASIC ethernet switch block.
B. A. KrishnaAnamaya SullereyAlok JainPublished in: FMCAD (2010)
Keyphrases
- formal verification
- high speed
- functional verification
- model checking
- model checker
- automated verification
- bounded model checking
- application specific
- symbolic model checking
- integrated circuit
- hardware architecture
- temporal logic
- design methodology
- low power
- single chip
- image blocks
- block size
- hardware implementation
- tcp ip
- artificial intelligence
- data acquisition
- general purpose