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Design of a compact chip filter with two transmission zeros using 0.35 μm GaAs HBT.
Shanwen Hu
Kaikai Xu
Yunqing Hu
Kejun Wu
Jinchao Qian
Yiting Gao
Dingzhou Song
Zixuan Wang
Bo Zhou
Zhikuang Cai
Yufeng Guo
Published in:
Microelectron. J. (2020)
Keyphrases
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case study
high speed
user interface
circuit design
single chip
neural network
design methodology
high density
programmable logic
chip design