Automatic bus macro placement for partially reconfigurable FPGA designs.
Jeffrey M. CarverRichard Neil PittmanAlessandro ForinPublished in: FPGA (2009)
Keyphrases
- hardware implementation
- field programmable gate array
- high speed
- low cost
- systolic array
- digital signal
- reconfigurable architecture
- real time
- semi automatic
- fully automatic
- single chip
- low power
- embedded systems
- image processing algorithms
- hardware design
- parallel architecture
- reconfigurable hardware
- data driven
- data sets