CMOS switched-op-amp-based sample-and-hold circuit.
Liang DaiRamesh HarjaniPublished in: IEEE J. Solid State Circuits (2000)
Keyphrases
- circuit design
- high speed
- analog vlsi
- delay insensitive
- vlsi circuits
- low voltage
- cmos technology
- low power
- chip design
- power consumption
- power dissipation
- low cost
- sample size
- randomly selected
- nm technology
- real time
- electronic circuits
- asynchronous circuits
- focal plane
- single chip
- artificial neural networks
- image sequences