A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOS.
Joseph F. RyanBenton H. CalhounPublished in: CICC (2010)
Keyphrases
- high speed
- metal oxide
- low power
- low cost
- inversely proportional
- cmos technology
- power consumption
- power reduction
- single chip
- power dissipation
- low power consumption
- real time
- nm technology
- hd video
- focal plane
- primal dual
- metal oxide semiconductor
- threshold selection
- low voltage
- software implementation
- field programmable gate array
- analog vlsi
- signal processing
- data acquisition