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Compact ASIC implementation of the ICEBERG block cipher with concurrent error detection.

Huiju ChengHoward M. Heys
Published in: ISCAS (2008)
Keyphrases
  • error detection
  • error correction
  • hardware implementation
  • error recovery
  • fault tolerance
  • design methodology
  • data cleansing
  • hardware architecture
  • block cipher
  • fault isolation
  • neural network
  • high dimensional