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An expandable topology with low wiring congestion for silicon interposer-based network-on-chip systems.
Sajed Dadashi
Midia Reshadi
Akram Reza
Ahmad Khademzadeh
Published in:
Trans. Emerg. Telecommun. Technol. (2019)
Keyphrases
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low cost
high density
intrusion detection
computer systems
model checking
network on chip