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A 3.3-V power adaptive 1244/622/155 Mbit/s transceiver for ATM, SONET/SDH.

Didier BelotLaurent DugoujonS. Dedieu
Published in: IEEE J. Solid State Circuits (1998)
Keyphrases
  • data aggregation
  • single chip
  • power consumption
  • low power
  • frequency response
  • power allocation
  • image processing
  • data driven
  • atm networks
  • database