Low-power design of sequential circuits using a quasi-synchronous derived clock.
Xunwei WuJian WeiMassoud PedramQing WuPublished in: ASP-DAC (2000)
Keyphrases
- low power
- high speed
- logic circuits
- power consumption
- power dissipation
- single chip
- cmos technology
- power reduction
- mixed signal
- low cost
- vlsi architecture
- low power consumption
- vlsi circuits
- digital signal processing
- gate array
- delay insensitive
- general purpose
- high power
- design process
- digital circuits
- design methodology
- multi channel
- wireless transmission
- real time
- digital camera
- nm technology
- ultra low power