FPGA architecture for noise filters on a reconfigurable processor.
Philip P. DangPaul M. ChauPublished in: CATA (1999)
Keyphrases
- systolic array
- xilinx virtex
- hardware implementation
- parallel architecture
- field programmable gate array
- fpga device
- digital signal
- general purpose processors
- hardware architecture
- reconfigurable hardware
- data flow
- high speed
- median filter
- fpga implementation
- processing elements
- low cost
- hardware design
- functional units
- dedicated hardware
- fpga technology
- software implementation
- morphological filters
- memory management
- parallel processing
- hardware architectures
- pipelined architecture
- impulsive noise
- wiener filter
- single chip
- computation intensive
- real time
- signal processing
- bandpass
- noise level
- filtering method
- embedded systems
- noise reduction
- signal to noise ratio
- distributed memory
- gate array
- efficient implementation
- level parallelism
- multi processor
- industry standard
- instruction set
- smart camera
- noise suppression
- noise removal
- nonlinear filters