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Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units.

Houman HomayounAvesta SasanAseem GuptaAlexander V. VeidenbaumFadi J. KurdahiNikil D. Dutt
Published in: Conf. Computing Frontiers (2010)
Keyphrases
  • high speed
  • random access memory
  • control system
  • parallel processing
  • low power
  • high level synthesis
  • single chip
  • neural network
  • optimal control
  • computer architecture
  • power reduction