An on-chip testbed that emulates runtime traffic and reduces design verification time for FPGA designs.
Wayne ChenLesley ShannonPublished in: FPT (2008)
Keyphrases
- single chip
- high speed
- functional verification
- low cost
- design space
- hardware design
- real time
- design tools
- creative design
- low power consumption
- physical design
- design principles
- formal methods
- case study
- design space exploration
- design methodology
- design process
- printed circuit boards
- design requirements
- programmable logic
- traffic flow
- low power
- network traffic
- application specific integrated circuits