A Reconfigurable 1 GSps to 250 MSps, 7-bit to 9-bit Highly Time-Interleaved Counter ADC with Low Power Comparator Design.
Seyed DaneshJed HurwitzKeith FindlaterDavid R. RenshawRobert K. HendersonPublished in: IEEE J. Solid State Circuits (2013)
Keyphrases
- analog to digital converter
- low power
- low cost
- single chip
- mixed signal
- high speed
- power consumption
- low power consumption
- nm technology
- power reduction
- image sensor
- logic circuits
- vlsi architecture
- digital signal processing
- power dissipation
- wireless transmission
- high power
- vlsi circuits
- cmos image sensor
- efficient implementation
- gate array