A 4-GHz all digital fractional-N PLL with low-power TDC and big phase-error compensation.
Ja-Yol LeeMi-Jeong ParkByonghoon MhinSeongdo KimMoon-Yang ParkHyunku YuPublished in: CICC (2011)
Keyphrases
- low power
- error compensation
- high speed
- mixed signal
- power consumption
- low cost
- vlsi circuits
- high power
- single chip
- wireless transmission
- digital signal processing
- low power consumption
- real time
- multi channel
- image sensor
- cmos image sensor
- cmos technology
- vlsi architecture
- structured light
- power reduction
- delay insensitive
- power saving
- signal processor
- phase shifting
- logic circuits
- denoising
- d objects