A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip.
Zhixiang ChenXiao PengXiongxin ZhaoLeona OkamuraDajiang ZhouSatoshi GotoPublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2011)
Keyphrases
- low density parity check
- ldpc codes
- high speed
- physical layer
- distributed source coding
- random access memory
- turbo codes
- distributed video coding
- decoding algorithm
- error correction
- floating point arithmetic
- channel coding
- low cost
- compressive sensing
- message passing
- low complexity
- floating point
- successive approximation
- wireless communication
- rate allocation
- error resilience
- image transmission
- application layer
- high density
- error resilient
- multipath
- low power
- random projections
- vlsi implementation
- video compression
- bitstream
- source coding
- motion estimation
- bit budget
- temporal correlation
- video codec
- error concealment