A Formal Method for the Specification, Analysis, and Design of Register-Transfer Level Digital Logic.
Louis J. HaferAlice C. ParkerPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1983)
Keyphrases
- significant improvement
- detection method
- high accuracy
- similarity measure
- high precision
- prior knowledge
- pairwise
- experimental evaluation
- computational complexity
- synthetic data
- high level
- formal methods
- cost function
- statistical analysis
- support vector machine svm
- design process
- objective function
- segmentation method
- range images