Login / Signup
A 12-b 4-MS/s SAR ADC With Configurable Redundancy in 28-nm CMOS Technology.
Stefan Hänzsche
Sebastian Höppner
Georg Ellguth
René Schüffny
Published in:
IEEE Trans. Circuits Syst. II Express Briefs (2014)
Keyphrases
</>
cmos technology
low power
spl times
parallel processing
power consumption
low voltage
sar images
single chip
silicon on insulator
low cost
image sensor
power dissipation
mixed signal
high speed
real time
dynamic range
pattern recognition