Switching protocol synthesis for temporal logic specifications.
Jun LiuNecmiye OzayUfuk TopcuRichard M. MurrayPublished in: ACC (2012)
Keyphrases
- temporal logic
- model checker
- model checking
- concurrent systems
- transition systems
- reactive systems
- modal logic
- bounded model checking
- satisfiability problem
- symbolic model checking
- formal verification
- formal specification
- formal specification language
- linear temporal logic
- protocol specification
- epistemic logic
- computation tree logic
- mazurkiewicz traces
- verification method
- predicate logic
- formal methods
- finite state
- belief revision
- automata theoretic
- temporally extended goals
- state space
- video sequences