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A 90 μW, 2.5 GHz high linearity programmable delay cell for signal duty-cycle adjustment.
Tobias Schirmer
Mohammad Mahdi Khafaji
Jan Plíva
Frank Ellinger
Published in:
SoCC (2019)
Keyphrases
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duty cycle
clock frequency
real time
power consumption
general purpose
low cost
parallel computing
high speed
parallel architecture
high end