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High-Performance Acceleration of 2-D and 3-D CNNs on FPGAs Using Static Block Floating Point.
Hongxiang Fan
Shuanglong Liu
Zhiqiang Que
Xinyu Niu
Wayne Luk
Published in:
IEEE Trans. Neural Networks Learn. Syst. (2023)
Keyphrases
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floating point
square root
fixed point
graphics processing units
instruction set
sparse matrices
floating point arithmetic
cellular neural networks
image sequences
interval arithmetic
bayesian networks
data structure
embedded systems
field programmable gate array