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A 16nm 256-bit wide 89.6GByte/s total bandwidth in-package interconnect with 0.3V swing and 0.062pJ/bit power in InFO package.

Mu-Shan LinChien-Chun TsaiKenny Cheng-Hsiang HsiehWen-Hung HuangYu-Chi ChenShu-Chun YangChin-Ming FuHao-Jie ZhanJinn-Yeh ChienShao-Yu LiY.-H. ChenC.-C. KuoShih-Peng TaiKazuyoshi Yamada
Published in: Hot Chips Symposium (2016)
Keyphrases
  • wide range
  • high speed
  • bit vector
  • neural network
  • computational power
  • low cost
  • logical operations