Parallel pipelined array architectures for real-time histogram computation in consumer devices.
José O. CadenasRobert Simon SherrattPablo HuertaWen-Chung KaoPublished in: IEEE Trans. Consumer Electron. (2011)
Keyphrases
- real time
- parallel computation
- linear array
- mobile devices
- low cost
- pipelined architecture
- parallel computers
- cell processor
- pc cluster
- parallel architectures
- parallel implementation
- parallel processing
- massively parallel
- shared memory
- multi core processors
- medical devices
- gray level
- real time systems
- parallel architecture
- embedded systems
- computer architecture
- multi threaded
- computer screen
- image retrieval