Model checking on TLM-2.0 IPs through automatic TLM-to-RTL synthesis.
Nicola BombieriFranco FummiValerio GuarnieriPublished in: VLSI-SoC (2010)
Keyphrases
- model checking
- temporal logic
- temporal properties
- automated verification
- finite state
- model checker
- finite state machines
- partial order reduction
- computation tree logic
- formal verification
- bounded model checking
- formal specification
- reachability analysis
- concurrent systems
- process algebra
- verification method
- symbolic model checking
- epistemic logic
- formal methods
- linear temporal logic
- transition systems
- timed automata
- pspace complete
- asynchronous circuits
- knowledge base
- reactive systems
- alternating time temporal logic
- modal logic