Login / Signup

A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process.

Dae-Hyun KimByungkyu SongHyun-a AhnWoongjoon KoSung-Geun DoSeokjin ChoKihan KimSeung-Hoon OhHye-Yoon JooGeuntae ParkJin-Hun JangYong-Hun KimDonghun LeeJaehoon JungYongmin KwonYoungjae KimJaewoo JungSeongil OSeoulmin LeeJaeseong LimJunho SonJisu MinHaebin DoJaejun YoonIsak HwangJinsol ParkHong ShimSeryeong YoonDongyeong ChoiJihoon LeeSoohan WooEunki HongJunha ChoiJae-Sung KimSangkeun HanJong-Min BangBokgue ParkJang-Hoo KimSeouk-Kyu ChoiGong-Heum HanYoo-Chang SungWonil BaeJeong-Don LimSeungjae LeeChangsik YooSang Joon HwangJooyoung Lee
Published in: ISSCC (2022)
Keyphrases
  • low power
  • high speed
  • high power
  • cmos technology
  • power consumption
  • low cost
  • low voltage
  • high density
  • vlsi architecture
  • wireless transmission
  • fourth generation
  • real time
  • main memory
  • vlsi circuits