A hardware efficient 3-bit second-order dynamic element matching circuit clocked at 300MHz.

Esmaeil Najafi Aghdam Philippe Bénabès

Published in: ISCAS (2006)

Keyphrases

high speed
low cost
low power
circuit design
dynamic environments
matching algorithm
feature matching
bit vector
hardware and software
parallel architectures
cmos technology
random number generator
real time
approximate matching
pattern matching
object recognition
neural network