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A 14.2 mW 2.55-to-3 GHz Cascaded PLL With Reference Injection and 800 MHz Delta-Sigma Modulator in 0.13 μ m CMOS.
Dongmin Park
SeongHwan Cho
Published in:
IEEE J. Solid State Circuits (2012)
Keyphrases
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delta sigma
analog to digital converter
high speed
power consumption
clock frequency
noise shaping
low power
delta sigma modulators
cmos technology
power supply
hd video
mixed signal
image sensor
high frequency
power dissipation
real time
error diffusion
image coding
gray scale
single chip