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Role of IC substrate and ESD protections in noise propagation: Design and modelling of dedicated test chip in 40 nm technology.
Mario Rotigni
Mauro Merlo
Martina Cordoni
Paolo Colombo
Valentino Liberali
Published in:
EMC Compo (2015)
Keyphrases
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nm technology
power consumption
built in self test
circuit design
low cost
integrated circuit
single chip
low power
design tools
power dissipation