Reliability aware NoC router architecture using input channel buffer sharing.
Mohammad Hossein NeishaburiZeljko ZilicPublished in: ACM Great Lakes Symposium on VLSI (2009)
Keyphrases
- network on chip
- multi processor
- routing algorithm
- network simulator
- packet switched
- multiple output
- management system
- software architecture
- wireless sensor networks
- input data
- multi channel
- data flow
- neural network
- program execution
- single processor
- data transfer
- end to end
- real time
- multiple input
- hardware implementation
- wireless networks