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A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm.
Chia-Tsun Wu
Wen-Chung Shen
Wei Wang
An-Yeu Wu
Published in:
IEEE Trans. Circuits Syst. II Express Briefs (2010)
Keyphrases
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estimation algorithm
phase locked loop
user friendly
preprocessing
user interface
computationally efficient
image segmentation
bit error rate
hadamard transform