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A Programmable Digital Neuro-Processor Design with Dynamically Reconfigurable Pipeline/Parallel Architecture.
Young-Jin Jang
Chan-Ho Park
Hyon-Soo Lee
Published in:
ICPADS (1998)
Keyphrases
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parallel architecture
high level synthesis
single chip
systolic array
parallel processing
hardware implementation
distributed memory
design process
shared memory
parallel implementation
high speed
design space
efficient implementation
processing elements
markov random field
neural network
functional verification