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Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI.
Sunghyun Park
Tushar Krishna
Chia-Hsin Owen Chen
Bhavya K. Daya
Anantha P. Chandrakasan
Li-Shiuan Peh
Published in:
DAC (2012)
Keyphrases
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silicon on insulator
cmos technology
network on chip
routing algorithm
ibm power processor
theoretical analysis
low power
high speed
power dissipation
parallel processing
low cost
d mesh
single chip
multi processor
tree structure
ad hoc networks
vlsi implementation
interconnection networks
analog vlsi
packet switched