High-level synthesis implementation of HEVC 2-D DCT/DST on FPGA.
Panu SjovallVili ViitamäkiJarno VanneTimo D. HämäläinenPublished in: ICASSP (2017)
Keyphrases
- high level synthesis
- parallel architecture
- hardware implementation
- discrete cosine transform
- hardware architecture
- fpga technology
- video compression
- efficient implementation
- parallel implementation
- transform domain
- hardware design
- hardware architectures
- case study
- image compression
- dedicated hardware
- xilinx virtex
- design space exploration