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A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue.

Hidehiro FujiwaraChih-Yu LinHsien-Yu PanCheng-Han LinPo-Yi HuangKao-Cheng LinJhon-Jhy LiawYen-Huei ChenHung-Jen LiaoJonathan Chang
Published in: ISSCC (2019)
Keyphrases
  • read write
  • power consumption
  • global optimization
  • answer questions
  • genetic algorithm
  • evolutionary algorithm
  • optimization process
  • disk drives
  • write operations