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0-40 GHz-Tunable RF Receivers on Chip exploiting a Noise-Cancelling Architecture and a Silicon Photonic Modulator.
Daniel Onori
Benjamin Crockett
Alireza Samani
David V. Plant
José Azaña
Published in:
OFC (2019)
Keyphrases
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high speed
sigma delta
low cost
cmos technology
high density
vlsi implementation
real time
low power
relevance feedback
radio frequency
host computer
parallel processing
analog vlsi
clock frequency
mixed signal
image coding
noise shaping