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Design issues and performance limitations of a clock jitter insensitive multibit DAC architecture for high-performance low-power CT Sigma Delta modulators.
Friedel Gerfers
Maurits Ortmanns
Yiannos Manoli
Published in:
ISCAS (1) (2004)
Keyphrases
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sigma delta
low power
design issues
image sensor
power consumption
high speed
low power consumption
signal processor
low cost
single chip
design decisions
high order
logic circuits
cmos technology
vlsi architecture
dynamic range
matlab simulink
medical images
digital camera
mixed signal
frame rate
real time