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Circuit-Simulation-Based Multi-objective Evolutionary Algorithm with Multi-Level Clock Driving Technique for a-Si: H TFTs Gate Driver Circuit Design Optimization.
Sheng-Chin Hung
Chieh-Yang Chen
Chien-Hsueh Chiang
Yiming Li
Published in:
ICS (2014)
Keyphrases
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high speed
duty cycle
cmos technology
thin film
multi objective evolutionary algorithms
low power
power consumption
neural network
artificial neural networks
genetic programming
driver assistance systems
low voltage
benchmark test
multi objective evolutionary