Evolutionary Fault Recovery in a Virtex FPGA Using a Representation that Incorporates Routing.

Jason D. Lohn Gregory V. Larchev Ronald F. DeMara

Published in: IPDPS (2003)

Keyphrases

hardware implementation
field programmable gate array
real time
genetic algorithm
fault diagnosis
ad hoc networks
high speed
reconfigurable hardware
neural network
sensor networks
shortest path
evolutionary computation
fault tolerance
phylogenetic trees