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Design of a Quaternary Latch Circuit Using a Binary CMOS RS Latch.
K. Wayne Current
Published in:
ISMVL (2000)
Keyphrases
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power consumption
low power
circuit design
power reduction
high speed
power dissipation
cmos technology
logic circuits
low cost
clock gating
flip flops
chip design
single chip
nm technology
design process
case study
engineering design
data sets