A 5.16Gbps decoder ASIC for Polar Code in 16nm FinFET.
Xiaocheng LiuQifan ZhangPengcheng QiuJiajie TongHuazi ZhangChangyong ZhaoJun WangPublished in: CoRR (2018)
Keyphrases
- reed solomon
- error control
- ldpc codes
- low complexity
- error correction
- integrated circuit
- source code
- xilinx virtex
- design methodology
- frequency domain
- fourier transform
- error detection
- single chip
- turbo codes
- error concealment
- noisy channel
- rotation invariant
- low density parity check
- physical design
- application specific
- hardware implementation
- convolutional codes