On-chip decoupling architecture with variable nMOS gate capacitance for security protection.

Radu Muresan Matthew Mayhew

Published in: MWSCAS (2013)

Keyphrases

security protection
cmos technology
high speed
low power
nm technology
power dissipation
analog vlsi
low cost
power consumption
vlsi implementation
network security
input output
single chip
host computer
databases
dynamic logic
real time
memory access
multithreading
network on chip
management system
cmos image sensor